1. Field of the Invention
The present invention generally relates to a nonvolatile semiconductor memory device such as an EPROM (erasable programmable read only memory), EEPROM (electrically erasable programmable read only memory) and a flash memory. More particularly, it relates to a method of making a nonvolatile memory device having a high capacitive coupling ratio.
2. Description of the Related Arts
High-density nonvolatile memory devices have been receiving much attention for application in many fields. One of the most important factors is the low cost of the reduced size of each memory cell. However, it is very difficult to shrink the cell size in the fabrication of nonvolatile memory cells when the conventional local oxidation (LOCOS) isolation technique is used. The isolation structure formed by this technique has a very large dimension and thus limits the miniaturization of the memory cells.
Another isolation technique called shallow trench isolation (STI) has been introduced to the fabrication of nonvolatile memory devices to reduce the cell size. The conventional field oxides are replaced by STI structures so that the device integration can be effectively improved. However, as component dimensions continue to shrink, the surface area of floating gates also shrinks. This leads directly to a decrease in capacitance of the effective capacitor formed between the floating gate layer and the control gate layer. This decrease in effective capacitance results in a reduction of the capacitive coupling ratio, which is a parameter that describes the coupling to floating gate of the voltage applied to control gate. The poorly-coupled voltage to floating gate limits the programming and accessing speed characteristics of the memory device.
The capacitive coupling ratio Cp is defined by:   Cp  =      Ccf          Ccf      +      Cfs      
where Ccf is capacitance between the control gate and the floating gate; and Cfs is capacitance between the floating gate and the semiconductor substrate.
In order to gain programming and accessing speeds in nonvolatile memories, many attempts have been done to increase the coupling ratio. It can be understood from the above equation that when the capacitance Ccf between the control gate and the floating gate increases, the coupling ratio Cp increases. Therefore, the coupling ratio Cp is generally increased by increasing the capacitor area between the floating gate and control gate, which increases the capacitance Ccf, and therefore the coupling ratio Cp.
U.S. Pat. No. 6,153,494 discloses a method to increase the coupling ratio by lateral coupling in stacked-gate flash memory cell. High-step oxides are formed protruding over the shallow trench isolation (STI). A polysilicon layer for serving as a floating gate layer is conformally deposited so as to follow the contours of an opening between the high-step oxides, thus providing addition surface to the control gate and increasing the coupling ratio. However in this method, the floating gate is not formed in a self-aligned manner. It requires an additional lithography and etching process to define the floating gate from the polysilicon layer, which inevitably incurs more cost and decreases the throughput, and possibly creates alignment errors.
Therefore, it would represent a significant advancement in the state of the art if the capacitive coupling ratio can be increased by forming a self-aligned floating gate.
An object of the invention is to provide a method of making a nonvolatile memory having a high capacitive coupling ratio.
Another object of the invention is to provide a method of making a nonvolatile memory having a self-aligned floating gate.
The above objects are accomplished by providing method of making a nonvolatile memory, comprising the steps of: sequentially forming a tunnel dielectric layer and a first conductive layer over a semiconductor substrate; forming a sacrificial layer over the first conductive layer; patterning the sacrificial layer, the first conductive layer, the tunnel dielectric layer, and the substrate to form trenches in the substrate; filling the trenches with isolation oxides that protrude over the substrate; removing the sacrificial layer thereby leaving a cavity between the isolation oxides; forming a second conductive layer conformally over the isolation oxides and along the sidewalls and bottom of the cavity; removing portions of the second conductive layer over the isolation oxides, wherein the remaining portions of the second conductive layer and the first conductive layer together serve as a floating gate layer; etching back the isolation oxides to expose additional surface of the second conductive layer; and sequentially forming an inter-gate dielectric layer and a control gate layer over the substrate.